1. Field of the Invention
The present invention relates to a modulator employing an oversampling ΔΣ converting method, which has been widely used in A/D (Analog-to-Digital) converters and D/A (Digital-to-Analog) converters for an audio band or range. Particularly, the invention relates to a modulator, which can reduce suppression of an input signal in a high order, and thereby can achieve high precision and improved stability in this conversion method.
2. Description of the Background Art
Modulators of an oversampling ΔΣ conversion method are now widely used for A/D converters and D/A converters, which may be referred to as “ADCs” and “DACs” hereinafter, respectively, for the audio band. As will be described later, the oversampling ΔΣ modulator is formed of a delay element, an integrator, an adder and a quantizer.
Japanese Patent Laying-Open Nos. 3-22626, 11-308110, 6-53836 and 2002-76902 have disclosed inventions relating to the above technology.
Japanese Patent Laying-Open No. 3-22626 has disclosed a fourth ΔΣ converter, which is formed of a primary loop and secondary loops. An output F of the main loop is expressed by the following formula:F=X(z)+(1−z−1)2·Q1(z)  (1)where X(z) represents an input signal, and Q1(z) represents quantization noises of a first quantizer.
If the first quantizer is formed of a simple comparator, the following relationship is present between its input E and output F:F=E+Q1(z)  (2)−Q1(z)=E−F  (3)
In the secondary loop, a quantization error −Q1(z) is integrated according to secondary transfer characteristics. A quantization output G is expressed by the following formula:G=−Q1(z)+(1−z−1)2·Q2(z)  (4)where Q2(z) expresses quantization noises of a second quantizer.
In this secondary loop, first and second differentiators are arranged downstream from the secondary quantizers, and differentiate quantization output G twice. An output H after the two differentiating operations is as follows:H=−(1−z−1)2·Q1(z)+(1−z−1)4·Q2(z)  (5)where (1−z−1) represents a transfer function of the first and second differentiators.
By adding this output H of the secondary loop to output F of the primary loop, (1−z−1)2·Q1(z) in the formula (1) cancels (−(1−z−1)2·Q1(z)) in the formula (5) so that a final output Y(z) is expressed by the following formula:Y(z)=X(z)+(1−z−1)4·Q2(z)  (6)
In this manner, the ΔΣ converter of a quadruple-integration type is equivalently achieved.
Japanese Patent Laying-Open No. 11-308110 has disclosed a ΔΣ-type A/D converter, which includes a plurality of cascaded delta-sigma loops for noise shaving and reduction of quantization noises.
Japanese Patent Laying-Open No. 6-53836 has disclosed an analog-to-digital converter circuit, which performs multiplication with (a≦1) by a factor multiplier, and performs restoration to an original size by the factor multiplier so that an input signal applied to the integrator of the delta-sigma A/D converter loop for the correction may be reduced.
Japanese Patent Laying-Open No. 2002-76902 has disclosed a prior art, in which a decimation filter arranged in a downstream position removes a noise power distributed outside an signal band.
As will be described later, an effect by modulation depends on the number of bit of the quantizers, or the number (order) of the feedback stages following the output of the integrator and quantizer. Thus, a higher order of the feedback stage increases the effect by the modulation if the number of bits of the quantizer is constant, and thus can achieve more precise modulation. However, a higher order of the modulator may excessively increase an amplitude of an output of the integrator in the final stage, resulting in a problem that large oscillation occurs.
In any one of the foregoing prior arts, since an original signal is provided to the modulator of the primary loop, the foregoing problems cannot be overcome.